Two's complement & signed numbers
There is no minus-sign wire inside a chip. This is how negatives are encoded in bits — the scheme every modern CPU uses, because the same adder just works.
Built from first principles. (The MPU6050 reports its accelerometer and gyro readings as 16-bit two's-complement values.)
Before you start
What you need first
- Base conversions — reading binary by place value.
- Binary addition — the flip step ends with "add 1", and the sanity-check is a binary sum.
What you'll be able to do
- Negate a number in two's complement (flip + add 1).
- Read any two's-complement value, positive or negative.
- State the range for a given width and recognise signed overflow.
How do we store a negative number?
So far our binary numbers have been unsigned — zero and positive only. But engineering is full of negatives: a sensor reading −40 °C, signed g-force, an audio sample swinging below zero, the difference of two readings.
Inside the chip there is still only 0 and 1 — no minus-sign
wire. So the sign must be encoded in the bits. Three schemes were tried
historically; the third one won.
| Scheme | Idea | Verdict |
|---|---|---|
| Sign-magnitude | MSB = sign, rest = magnitude | Two zeros (+0, −0); messy addition |
| 1's complement | Negate by flipping every bit | Still two zeros; "end-around carry" quirk |
| 2's complement | Flip, then add 1 | One zero; the same adder just works ✓ |
Two's complement — how to negate
To get the representation of a negative number, do two steps:
- Flip every bit (0↔1 — this is the 1's complement).
- Add 1.
Negate +5 in 8 bits
−5 = 11111011 in 8-bit two's complement.✏️ Try it yourself
Convert −7 to 8-bit two's complement.
00000111.
Flip: 11111000.
Add 1: 11111001.
Answer: −7 = 11111001.
Why two's complement is brilliant
Sanity check: +5 + (−5) should be 0.
The 9th bit is the carry-out; in 8-bit arithmetic it is simply discarded.
What remains is 00000000 = 0. ✓
00000000) — no "two zeros" headache.The range of values
For an \(n\)-bit two's-complement number the MSB still signals the sign (0 = positive, 1 = negative), and the range is asymmetric — one extra negative value:
| Width | Signed range | Unsigned range |
|---|---|---|
| 8-bit | −128 … +127 | 0 … 255 |
| 16-bit | −32768 … +32767 | 0 … 65535 |
| 32-bit | −2147483648 … +2147483647 | 0 … 4294967295 |
Reading a two's-complement value
Always check the MSB first.
What value is 00001101?
MSB is 0 → positive → read it as ordinary binary:
What value is 11110011?
MSB is 1 → negative → negate it (flip + add 1), read that, put the minus back:
✏️ Try it yourself
What decimal value is 11110001, read as 8-bit two's complement?
11110001 → 00001110 → 00001111 = 15.
Answer: 11110001 = −15.
Signed overflow — a real source of bugs
If a result won't fit the width, it wraps:
We wrapped from +127 straight to −128.
- Ariane 5 (1996): rocket destroyed 39 s after launch — a 64-bit float forced into a 16-bit signed integer overflowed.
- Boeing 787: needed a reboot every 248 days — a 32-bit signed counter ticking every 10 ms overflowed (\(2^{31}\) ticks × 10 ms ≈ 248 days).
Recap — the whole topic on one screen
| Idea | What you own now |
|---|---|
| Negate | Flip every bit, then add 1 |
| Read | MSB 0 → read as binary; MSB 1 → negate, read, add minus |
| Range (n-bit) | \(-2^{n-1}\) … \(+2^{n-1}-1\) (8-bit: −128…+127) |
| Why it wins | One zero; the same adder handles + and − |
| Overflow | Result wraps; choose a wide-enough type |