The combinational design method
You can read, write, and minimise logic. Now turn a sentence into a circuit — with a four-step recipe that works every time and scales to the whole ALU.
Built from first principles.
Before you start
What you need first
- English → Boolean — turning a requirement into a logic statement.
- Truth tables & canonical forms — listing every input case as SOP.
- K-maps — minimising the expression you read off the table.
What you'll be able to do
- State the four steps of combinational design.
- Take a plain-English spec all the way to a gate circuit.
- Know where the truth table and K-map fit in the flow.
First: what "combinational" means
A combinational circuit's output depends only on its inputs right now — no memory, no clock, no history. Give it the same inputs and you always get the same output. (Circuits that remember come later, in Theme 5.)
The four-step recipe
Never jump straight from a requirement to gates — you'll miss cases and build something bigger than needed. Always walk these four steps in order:
| Step | What you do | Tool |
|---|---|---|
| 1 · Specify | Write exactly when the output is 1, in plain words. | English → Boolean |
| 2 · Truth table | List every input combination and its output. Nothing is left ambiguous. | truth table |
| 3 · Simplify | Read the SOP off the 1-rows, then minimise it. | algebra or K-map |
| 4 · Draw | Translate the minimal expression into gates (or write HDL). | gate symbols / Verilog |
Design: "output is 1 when exactly one input is high"
Step 1 — Specify. Two inputs A, B. Output
Y = 1 when exactly one of them is 1 (not both, not neither).
Step 2 — Truth table. Write all four rows:
| A | B | Y |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
Step 3 — Simplify. Read the SOP from the two 1-rows (row 01 gives
A′·B, row 10 gives A·B′):
Only two terms, no shared variable to factor — this is already minimal. (A K-map would show two single cells that cannot be grouped.)
Step 4 — Draw. That expression is the well-known
exclusive-OR, A ⊕ B — so common it has its own symbol:
The raw form needs two NOTs, two ANDs and an OR. Recognising it as A ⊕ B
collapses it to a single gate.
Why this matters for the rest of the theme
Every block in this theme — the adder, the comparator, the multiplexer, the decoder, even the ALU — is just this method applied to a bigger spec. Once a block is designed and tested, you treat it as a single labelled box and wire boxes together. That habit, building bigger blocks from tested smaller ones, is called hierarchical design, and it runs through all of engineering.
✏️ Try it yourself
(a) List the four steps in order. (b) Which step produces a complete, unambiguous spec?
(c) At which step do you use a K-map? (d) "Y = 1 only when both inputs are 1."
Give the truth table output column (rows 00, 01, 10, 11) and the expression.
0,0,0,1; expression Y = A·B (a single AND gate).
Recap — the whole topic on one screen
| Idea | What you own now |
|---|---|
| Combinational | output depends only on present inputs — no memory |
| The method | specify → truth table → simplify → draw |
| Truth table | the complete spec; written before any optimising |
| K-map's place | step 3 only — minimise, don't specify |
| Hierarchical design | tested blocks become boxes you wire together |