CE2704 · Digital Logic Design
Theme 4 · Combinational building blocks

The ripple-carry adder

One full adder handles one column. Line several up — each carry feeding the next — and you can add whole numbers, exactly the way you add on paper.

Built from first principles.

Before you start

What you need first

  • The full adder — the FA cell with A, B, Cin → Sum, Cout.
  • Binary addition — carrying from one column to the next.

What you'll be able to do

  • Build an n-bit adder by chaining n full adders.
  • Add two binary numbers through the chain, tracking the carry.
  • Explain why it's called "ripple" — and the speed cost that name hides.

Chaining: one FA per column

Adding on paper, you work column by column, passing each carry left into the next column. The circuit does the same: one full adder per bit, with each stage's Cout wired into the next stage's Cin. The very first carry-in is 0 (nothing to carry into the lowest column).

FA0 FA1 FA2 FA3 A0B0S0 A1B1S1 A2B2S2 A3B3S3 C0C1C2 0Cout
A 4-bit ripple-carry adder: four FA cells, LSB on the left. Each carry (C0, C1, C2) ripples into the next stage; the first carry-in is 0.
To make an 8-, 16-, or 32-bit adder you change nothing about the design — you just add more identical FA stages. That's the power of a reusable block.
📐 Worked example

Add 0110 + 0011 (6 + 3) on a 4-bit ripple adder

Work the stages from the LSB (bit 0) upward, carrying each C into the next:

StageAiBiCinSumCout
bit 001010
bit 111001
bit 210101
bit 300110

Reading the Sum bits from bit 3 down to bit 0, with the final carry-out on the far left:

$$ \text{Sum} = 1001_2 = 9,\qquad C_{out} = 0 $$
6 + 3 = 9. ✓ The carry-out is 0, so the answer fits in 4 bits with no overflow.

Why "ripple" — and the catch

Look at the chain again: stage 1 can't finish until it knows C0 from stage 0; stage 2 waits on C1; and so on. The carry has to ripple all the way from the lowest stage to the highest before the answer is final.

Each full adder takes a little time to settle — say 2 ns of carry delay. For a wide adder the delays add up in series:

$$ \text{16-bit worst-case delay} = 16 \times 2\,\text{ns} = 32\,\text{ns} $$
The trade-off: a ripple-carry adder is small, simple, and easy to extend — but slow for many bits, because the delay grows with the number of stages.

🔭 Looking ahead. Designers fix the speed problem with a carry-lookahead adder, which computes all the carries in parallel instead of waiting for them to ripple. You don't need its details now — just know that "make the carry faster" is the next step up, and the ripple adder is where everyone starts.

✏️ Try it yourself

(a) What connects one full-adder stage to the next? (b) What is the carry-in to the very first stage? (c) Add 0101 + 0011 (5 + 3) on a 4-bit ripple adder — give the 4-bit sum and Cout. (d) If one FA has 2 ns of carry delay, what is the worst-case delay of an 8-bit ripple adder?

(a) each stage's Cout wires into the next stage's Cin. (b) 0. (c) 5 + 3 = 8 = 1000, Cout = 0. (d) 8 × 2 ns = 16 ns.

Recap — the whole topic on one screen

IdeaWhat you own now
n-bit addern full adders in a chain, Cout → next Cin
First carry-inalways 0
Scales byadding identical FA stages — design unchanged
"Ripple"carry must propagate LSB → MSB before the answer is valid
Costdelay grows with bit-width; carry-lookahead is the faster fix

Next topic

The adder/subtractor

An adder only adds — or does it? With two's complement and one row of XOR gates, the very same chain can subtract too, switched by a single control bit.

→ The adder/subtractor